CEDEC 2026 Talk Maps the Three Valleys Blocking Next-Gen Consoles
The talk puts numbers on why the old console pattern, flat price and a leap in performance every generation, stops holding in the late 2020s.
Reporting from 1 source: Game Spark.
Technical journalist Zenji Nishikawa's CEDEC 2026 talk laid out why the console generation cycle is running out of room. Moore's Law has slowed, process node names have become nominal labels, and manufacturing costs jump at the 3nm, 2nm, and 1nm generations. A 3nm next-gen console would reach roughly 30 to 40 teraFLOPS, about three times PS5, priced near $640 to $760. The CFET-generation successor would top 100 teraFLOPS, about one high-end GPU.
The cost pressure starts at the lithography step. EUV exposure tools come from a single maker, ASML, at roughly 50 billion yen each, about 50 units a year. The High-NA EUV tools needed for the CFET generation cost 70 to 100 billion yen, and only about 10 are made annually. Double patterning, where one wiring layer needs multiple exposures, pushes the cost of a same-area chip at 3nm and beyond to two to three times the pre-4nm level.
Nishikawa's estimates follow from those constraints. A 3nm console lands at 30 to 40 teraFLOPS, about three times PS5, at $640 to $760. The CFET-generation machine exceeds 100 teraFLOPS, roughly one high-end GPU. Power is the second wall: a 2035 flagship GPU alone draws 700 to 800 watts, pushing a full system past 1000 watts.
Synthesized by Yomimono from the 1 cited source below, including Japanese-language reporting where cited, then editorially reviewed before publishing.