IBM Successfully Manufactures a 0.7nm Chip Using Staggered CFET Structure
IBM is the only company to publicly adopt the staggered CFET design, and the 0.7nm milestone shows a concrete step beyond current process nodes, though manufacturing costs and performance verification remain open questions.
Reporting from 1 sources: ASCII.jp.
IBM announced on June 26, 2026, that it has successfully manufactured a chip using a 0.7nm process. The chip uses a staggered CFET transistor structure called NanoStack, which IBM claims can increase effective channel width by up to 65%. The announcement was made via a press release and online briefing, though actual performance confirmation is still pending.
IBM announced on June 26 that it has fabricated a chip using a 0.7nm process, the smallest node yet publicly demonstrated. The test chip uses a staggered CFET transistor architecture the company calls NanoStack, which it says can increase effective channel width by up to 65% compared to an aligned design. The underlying structure was first presented at the 2025 VLSI Symposium. IBM held an online briefing alongside the release, but the company has not disclosed the chip's contents beyond noting it integrates test circuits and likely includes multiple SRAM blocks. Performance confirmation is still pending, and the announcement language around verified operation may be marketing, according to the report.
Synthesized by Yomimono from the 1 cited source below, including Japanese-language reporting where cited, then editorially reviewed before publishing.