Intel's Wildcat Lake Drops Foveros for MCP to Cut Costs
Wildcat Lake's packaging shows Intel prioritizing cost over the flexibility of Foveros, pairing a reused Intel 18A compute tile with a TSMC N6 controller tile and a deliberately cautious UCIe debut.
Reporting from 1 source: ASCII.jp.
Intel detailed Wildcat Lake at Hot Chips, confirming the processor abandons the Foveros packaging used since Meteor Lake for a two-tile MCP. The CPU and GPU tile runs on Intel 18A with Cougar Cove P-cores, while the Platform Controller Tile moves to TSMC N6. The tiles connect over UCIe, Intel's first product use of the interface, held to a conservative 8Gbps to control bit error rates.
Intel weighed a monolithic design for Wildcat Lake and passed on it. A single die would remove the D2D PHY, but the larger die would cut yield and push I/O buffers onto a more expensive process node, so the MCP route won on cost despite the added PHY area.
The one gamble is UCIe, the interface linking the CPU and GPU tile to the Platform Controller Tile. It is Intel's first product use of the standard, and the signal rate is capped at 8Gbps because faster links pushed bit error rates past acceptable limits, requiring retry and FEC logic that would add complexity and schedule risk.
Synthesized by Yomimono from the 1 cited source below, including Japanese-language reporting where cited, then editorially reviewed before publishing.