Samsung Prototypes Next-Generation CFET for Mass Production
Samsung's CFET prototype offers a mass-production-oriented alternative to IBM's expensive CFET method, signaling a focus on practical scaling for future nodes.
Reporting from 1 source: ASCII.jp.
Samsung has prototyped a next-generation CFET (3DSFET) with a 42nm gate pitch and triple stacked nanosheet channels, its third such prototype. The company's batch formation process is designed for mass production, contrasting with IBM's costly method. The prototype was presented at the 2026 VLSI Symposium. Samsung's foundry roadmap shows SF2P yield improvement and resumed SF1.4 development, with CFET as the next step.
Samsung presented its third CFET prototype at the 2026 VLSI Symposium, this time with a 42nm gate pitch and triple stacked nanosheet channels. The company's previous prototypes in 2024 and 2025 focused on basic structures; this year's version is limited to transistors, with inverter and SRAM demonstrations expected next year.
The prototype uses a batch formation process aimed at mass production, a direct contrast to IBM's CMOS 7A method, which the article notes carries a $100,000 per wafer cost. Samsung's foundry division has been working to recover from yield issues with its SF3 and SF2 nodes. After freezing SF1.4 development in early 2025 to improve SF2 yield, the company resumed SF1.4 work in June 2026, targeting mass production in 2029. CFET is positioned as the next-generation architecture beyond that.
Synthesized by Yomimono from the 1 cited source below, including Japanese-language reporting where cited, then editorially reviewed before publishing.