TSMC Develops Quasi-EMIB Packaging to Counter Intel EMIB
TSMC's Quasi-EMIB signals a direct response to Intel's EMIB gaining traction in AI packaging, while CoWoS capacity stays tight.
Reporting from 1 source: GIGAZINE.
TSMC is developing a new 2.5D packaging technology internally called Quasi-EMIB, based on Intel's EMIB, according to The Information. The technology is reportedly being developed jointly with substrate maker KINSUS. The move comes as Intel's EMIB gains order volume and TSMC's CoWoS remains constrained through 2026.
TSMC's CoWoS-L uses a separate RDL interposer with embedded local silicon interconnects, requiring two assembly and bonding processes. Intel's EMIB skips the interposer entirely, embedding fine silicon bridges directly in the organic substrate and placing micro-bumps only at chip-to-bridge edges. Intel's next-gen EMIB-T adds through-silicon vias for 3D stacking.
According to The Information, TSMC's Quasi-EMIB is based on Intel's approach and is being developed with KINSUS, a major packaging substrate manufacturer. Details remain unclear, but the project signals TSMC is adapting to competitive pressure in AI chip packaging.
Synthesized by Yomimono from the 1 cited source below, including Japanese-language reporting where cited, then editorially reviewed before publishing.