AMD Details Instinct MI400 Architecture and Helios Rack at Hot Chips 2026
AMD's split-chip MI400 layout, a larger HBM4 load and Ethernet-carried UALoE point to rack-scale link design as the contested ground in the next accelerator generation, rather than the single die.
Reporting from 1 source: ASCII.jp.
At Hot Chips 2026, AMD gave two talks on the Instinct MI400, covering the GPU's internal structure and the system architecture for the Helios rack. The MI400 moves the XCDs to TSMC N2 and the IODs to N3P, splits the Infinity Cache into a separate FCD, carries 12 HBM4 stacks, and adds 72 lanes of UALoE alongside PCIe, with PCIe, UALink and UALoE switched at the protocol level.
The Instinct MI400 totals 12 chiplets. Eight XCDs sit on top of the FCD, and the separate IOD connects alongside them.
The Infinity Cache drops from 256MB across the MI350 series to 192MB, split into 96 1MB blocks per FCD, with HBM4 capacity and bandwidth rising to compensate. Each XCD carries 34 WGPs with 32 enabled, giving 256 WGPs across the package, which AMD counts as the equivalent of 512 CUs. The LDS grows from 160KB to 384KB.
Written with AI by Yomimono from the 1 cited source below, including Japanese-language reporting where cited. See our editorial policy.
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