NVIDIA's Vera CPU Puts Olympus Core And A 10-Wide Decode Front End On The Table
Vera is NVIDIA's second data center CPU but the first place it puts a fully self-designed core, so the Olympus numbers mark how far the company has moved from the Neoverse V2 it licensed for Grace.
Reporting from 1 source: ASCII.jp.
A Hot Chips session on NVIDIA's Vera server chip walks through the custom Olympus core, which fetches 16 instructions per cycle and decodes and dispatches 10 per cycle across 18 issue ports. The design keeps the decode throughput of the earlier Arm AGI CPU but pairs it with instruction fusion inside the decode queue and different micro-ops, which the writeup reads as an IPC advantage. NVIDIA designed Vera's core itself, where the earlier Grace chip used Arm's Neoverse V2.
NVIDIA's Hot Chips talk on Vera went past the core count and into the pipeline. Olympus fetches 16 instructions per cycle, decodes and dispatches 10, and issues to 18 ports, with instruction fusion handled inside the decode queue and rename stages that carry move elimination and memory renaming.
Decode throughput matches the earlier Arm AGI CPU, but the micro-ops differ, and the writeup reads Olympus as the stronger core on instructions per cycle. The larger point is structural: Grace used Arm's Neoverse V2, so Vera is where NVIDIA's own core work, which ran through Project Denver and the Carmel-based Tegra T194 before continuing on RISC-V control cores, finally reaches a shipping data center part.
Synthesized by Yomimono from the 1 cited source below, including Japanese-language reporting where cited, then editorially reviewed before publishing.